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Count the whole register range of 64- and 128-bit loads and stores when the lowering places its uniform registers.

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The SM86 lowering keeps the uniform registers in the general registers after the highest one the program uses
(HighestGpr), with one spare so pairs stay aligned. The scan read the register fields as single registers, so a
128-bit load or store whose upper registers the program names nowhere else (LDG, LDS, LDL and STG, STS, STL with size
6) left Rd+2 and Rd+3 to UR0 and UR1, and the load overwrote them. The scan now counts Rd..Rd+3 (Rd..Rd+1 for 64 bits)
of these forms. An overestimate only moves the uniform registers up.

Checked: no translation changes in the game's 520 task and mesh programs, its 4,238 NVN2 compute programs, or the
2,450 vertex and fragment programs whose stored input id starts with 0, all from an installed shader cache, and all
pass spirv-val (vulkan1.3): the case does not occur in what this game version has shown so far.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
chrg6
2026-11-11 17:25:50 -05:00
parent 2cccdb8823
commit f39e5930d1
1 changed files with 7 additions and 0 deletions
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7
tools/xlate/AmpereLowering.cs
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@@ -196,6 +196,13 @@ static class AmpereLowering
uint k16 = i.Bits(75, 1), cd = i.Bit(76) ? 3u : 1u;
see(i.Bits(16, 8) + cd); see(i.Bits(24, 8) + 1 + 2 * k16); see(i.Bits(32, 8) + k16); see(i.Bits(64, 8) + cd);
}
// 64- and 128-bit loads write Rd..Rd+1 or Rd..Rd+3, the stores read Rb..Rb+1 or Rb..Rb+3 (size 73-75: 5, 6).
// A program that names only Rd of its highest quad would otherwise put UR0 and UR1 in its top registers.
if (op is 0x381 or 0x981 or 0x984 or 0x983 or 0x386 or 0x986 or 0x388 or 0x988 or 0x387 or 0x987)
{
uint size = i.Bits(73, 3), reg = op is 0x381 or 0x981 or 0x984 or 0x983 ? i.Bits(16, 8) : i.Bits(32, 8);
if (size is 5 or 6 && reg < RZ) see(reg + (size == 6 ? 3u : 1u));
}
if (op == 0x3a9) see(i.Bits(64, 8)); // ATOMG.CAS: the new value
if (op == 0x593 || (op == 0xb66 && i.Bit(78))) see(i.Bits(32, 8)); // SUATOM data, TLD.MS sample index
if (b < 0x080 || b is >= 0x160 and <= 0x16f) see(i.Bits(64, 8)); // C of ALU forms, TEX second destinations