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Order the write-back merge's writes after earlier writes of the imported buffers it writes.
The barrier before the merge (vk_memory.c vk_mem_mirror_end) made earlier writes visible to the merge's shader reads only; its shader writes to the imported buffers follow writes there too, and a write after a write needs the write access in the dependency's second scope. On for every device: the barrier was there already, it only covers one access more. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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@@ -4322,9 +4322,12 @@ int vk_mem_mirror_end(VkCommandBuffer cb, uint64_t fence) {
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int rec = 0;
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lazy_part_check(); // before the merges are recorded: what the last part skipped and has to write back after all
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if (nsnl) {
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// the merge reads the mirror the submission's shaders wrote and writes the imported buffers
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// the merge reads the mirror the submission's shaders wrote and writes the imported buffers, which earlier
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// commands may have written too: its writes are ordered after theirs as well (a write after a write needs the
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// write access on both sides of the dependency)
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mbarrier(cb, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT, VK_ACCESS_2_MEMORY_WRITE_BIT,
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VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, VK_ACCESS_2_SHADER_STORAGE_READ_BIT);
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VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
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VK_ACCESS_2_SHADER_STORAGE_READ_BIT | VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT);
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vk_gpu_gap_note(VK_GAP_WB_MERGE, 0);
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int m = wb_merge_record(cb);
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if (!m) { // no range list: copy them plainly
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