From 514bb8eaa9a0dd4983393a43d6583dfdbed6ce57 Mon Sep 17 00:00:00 2001 From: chrg6 Date: Sat, 7 Nov 2026 13:42:08 -0500 Subject: [PATCH] Translate the 8- and 16-bit uniform constant loads whose unused register field is 0, not 63. ULDC's immediate form (0xab9) has no register index; the sub-word path required the field to hold URZ, as the 32- and 64-bit paths do not, and compilers leave 0 there too. Of the game's 36,031 shaders, 40 more translate: 20 failures are left, all the lowering's room for uniform register groups. Co-Authored-By: Claude Opus 5.5 --- tools/xlate/AmpereLowering.cs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/xlate/AmpereLowering.cs b/tools/xlate/AmpereLowering.cs index aa9ed7db..c49c59e6 100644 --- a/tools/xlate/AmpereLowering.cs +++ b/tools/xlate/AmpereLowering.cs @@ -509,8 +509,10 @@ static class AmpereLowering int d = Ur((uint)Dst); if (width < 4) // U8, S8, U16, S16: Maxwell LDC with the same width code, immediate address (any alignment) { + // (this form, 0xab9, has no register index: bits 24-29 are not read, as for the 32- and 64-bit loads + // below; compilers leave 0 there as well as 63, and the 0 cases failed. 0xabb is the indexed form.) int cb = Bank(_i.Bits(54, 5)), at = (int)_i.Bits(38, 16); - if (cb >= 18 || at >= 0x8000 || _i.Bits(24, 6) != 63) throw Fail($"ULDC width {width} c[{_i.Bits(54, 5)}][0x{at:x}]"); + if (cb >= 18 || at >= 0x8000) throw Fail($"ULDC width {width} c[{_i.Bits(54, 5)}][0x{at:x}]"); if (d != RZ) EmitG(0xef90000000000000UL | ((ulong)RZ << 8) | ((ulong)at << 20) | ((ulong)cb << 36) | ((ulong)width << 48) | (uint)d); return;